1. Field of the Invention
The present invention relates to semiconductor memory devices and, more specifically, to a synchronous semiconductor memory device in which external signals are taken in in synchronization with external clock signals applied periodically. More specifically, the present invention relates to a synchronous type random access memory (DRAM) which requires refreshing operation.
2. Description of the Background Art
The speed of operation of a microprocessor (MPU) has been much increased recently. Although the speed of operation of a dynamic random access memory (hereinafter referred to as a DRAM) used as a main memory has been improved, it still can not follow the speed of operation of the MPU. Consequently, the performance of the whole system is degraded because of the access time and the cycle time of the DRAM being a bottle neck.
In order to improve system performance, a method is frequently used in which a high speed memory called a cache memory consisting of a high speed static random access memory (SRAM) is provided between the DRAM and the MPU. Data which are used highly frequently are stored in the cache memory, and if the data required by the MPU is stored in the cache memory, the high speed cache memory is accessed. The DRAM is accessed only when the data requested by the MPU is not in the cache memory. Since data which are frequently used are stored in the high speed cache memory, the frequency of accessing to the DRAM is significantly reduced, and accordingly, the influence of the access time and the cycle time of the DRAM can be removed, and the system performance can be improved.
The use of a cache memory is inexpedient for devices which are relatively inexpensive, such as personal computers, since SRAMs are much expensive than DRAMs. Therefore, it is desired to improve system performance by using inexpensive DRAMs.
If the MPU and the DRAM are to be simply operated in synchronization, a system clock may be applied to the DRAM so that the DRAM is operated in synchronization with the system clock. A structure in which the DRAM is operated in synchronization with the system clock signal is disclosed in U.S. Pat. No. 5,083,296 to Hara.
In the DRAM of Hara, a chip select signal /CS and a write enable signal /WE are latched in synchronization with a clock signal CLK. If the latched chip select signal /CS is active, indicating that the DRAM has been selected, an internal RAS signal and an internal CAS signal are generated in synchronization with the clock signal. In response to the internal RAS and internal CAS signals, an address signal is latched and an internal row address signal and an internal column address signal are generated. Input/output of data is also effected in synchronization with the clock signal CLK.
Hara aims to solve the problems such as variation of timings generated when the DRAM is operated in response to control signals such as the row address strobe signal RAS and the column address strobe signal CAS, by operating the DRAM in synchronization with the clock.
In Hara, only the clock synchronized operation of the DRAM is intended. The address signal is latched by the internal RAS signal and the internal CAS signal generated in synchronization with the clock signal CLK. A desired internal address signal can be generated in response to an external address signal in a case of a clock signal of relatively low speed or of an address signal having sufficient margins for setup time and hold time.
However, if the clock signal CLK is a high speed one or if the margins of the setup time and the hold time of the address signal are small, the internal address signal may possibly have been changed to the invalid state by the time the internal RAS signal and the CAS signal are generated. Therefore, the DRAM of Hara can not be operated in synchronization with a high speed clock signal. In other words, it can not be used as a high speed main memory for the high speed MPU. As for the internal structure, the DRAM of Hara has the similar structure as a common standard DRAM, and only difference is that latch circuits operated by clocks are provided at the input/output portions of external control signals and data.
JEDEC (Joint Electron Device Engineering Council) of the United States adopts a synchronous DRAM (hereinafter referred to as SDRAM) operating in synchronization with the clock signal as a main memory for a high speed MPU, and the specification of the SDRAM is now being standardized. Details of the standard specification have not yet been made public. According to Nikkei Electronics Feb. 3, 1992, p 85, the following structure has been proposed:
(1) Synchronous operation is done with the clock signal having the period of 10 to 15 ns (nano seconds). PA1 (2) In a first random accessing, data is accessed after 4 to 6 clocks after the input of a row address signal. Thereafter, data of successive addresses can be accessed clock by clock. PA1 (3) Circuitry in the chip is operated in the pipe line manner, and a serial input/output buffer is provided at the data input/output portion to reduce access time.
The above mentioned structure is simply a proposal, and specific methods for implementing such structure have not yet been disclosed at all.